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Proceedings Paper

Integration of Flowfill and Forcefill for cost-effective via applications
Author(s): Werner K. Robl; Juergen Foerster; Uwe Hoeckele; Manfred Frank; David Butler; Paul Rich; K. Beekmann
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Paper Abstract

This paper reviews work to integrate FlowfillTM planarizing dielectric with ForcefillTM aluminum plug in a 0.5/0.35 micrometers CMOS design. Work to reduce dielectric cracking by modifying the stress of the IMD material is described. The paper discusses liner choice for the ForcefillTM interconnect and how it can influence lithography accuracy, line resistance and electromigration. The use of via chain resistance as a test to determine the degree of metal hole-fill is described.

Paper Details

Date Published: 11 August 1999
PDF: 7 pages
Proc. SPIE 3883, Multilevel Interconnect Technology III, (11 August 1999);
Show Author Affiliations
Werner K. Robl, Infineon Technologies AG (Germany)
Juergen Foerster, Infineon Technologies AG (Germany)
Uwe Hoeckele, Infineon Technologies AG (Germany)
Manfred Frank, Infineon Technologies AG (Germany)
David Butler, Trikon Technologies, Ltd. (United Kingdom)
Paul Rich, Trikon Technologies, Ltd. (United Kingdom)
K. Beekmann, Trikon Technologies, Ltd. (United Kingdom)

Published in SPIE Proceedings Vol. 3883:
Multilevel Interconnect Technology III
Mart Graef; Divyesh N. Patel, Editor(s)

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