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Proceedings Paper

Sub-0.1-um vertical MOS transistor
Author(s): Kiyoshi Mori
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Paper Abstract

A sub 0.1 microns channel length vertical MOS transistor was developed for processing with equipment typically utilized for older generation devices. One of the important advantages of vertical MOS transistor technology is that the channel length scaling is not limited by the minimum lithographic resolution. The vertical Ldd processing was also developed to improve the short channel effects. The transistor with channel length below 0.1 micrometers has normal characteristics at room temperature, a > 6V Bvdss, and a transconductance with value as high as in the conventional planar transistor of the same channel length.

Paper Details

Date Published: 1 September 1999
PDF: 4 pages
Proc. SPIE 3881, Microelectronic Device Technology III, (1 September 1999); doi: 10.1117/12.360569
Show Author Affiliations
Kiyoshi Mori, Sony Semiconductor Co. (United States)

Published in SPIE Proceedings Vol. 3881:
Microelectronic Device Technology III
David Burnett; Toshiaki Tsuchiya, Editor(s)

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