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Proceedings Paper

Drain profile engineering for MOSFET devices with channel lengths below 100 nm
Author(s): Samar K. Saha
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Paper Abstract

This paper presents a systematic methodology to optimize the source-drain region of sub-100 nm MOSFET devices to design a high performance CMOS technology. The effect of most critical source-drain parameters such as the lateral and the vertical dimensions of shallow extensions, the junction depth of deep regions, and the strength and confinement of halo profiles on device performance are presented. The simulation results show that the shallower and the longer source=-drain extensions cause a significant degradation in drive current due to an increase in the source-drain series resistance while the deeper and the shorter extensions worsen the short-channel effect due to higher channel charge sharing with the source-drain regions. Similarly, the shallower deep source-drain regions cause performance degradation due to higher source-drain series resistance and deeper junctions cause higher channel charge sharing resulting in a higher short-channel effect. It is shown that the junction depth of shallow source-drain regions must be approximately 30-40 nm to design high performance sub-100 nm MOSFETs, and the short channel effect can be improved by a proper optimization of halo doping profiles around the source-drain extensions. The simulation results also show that the concentration and distribution of halo doping profiles must be optimized to obtain the target off-state leakage current for sub-100 nm CMOS technologies.

Paper Details

Date Published: 1 September 1999
PDF: 10 pages
Proc. SPIE 3881, Microelectronic Device Technology III, (1 September 1999); doi: 10.1117/12.360553
Show Author Affiliations
Samar K. Saha, VLSI Technology, Inc. (United States)

Published in SPIE Proceedings Vol. 3881:
Microelectronic Device Technology III
David Burnett; Toshiaki Tsuchiya, Editor(s)

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