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Proceedings Paper

Degradation of PMOS series resistance due to Si implantation for Ti-salicide process
Author(s): Eng-Hua Lim; Soh Yun Siah; Chong Wee Lim; Yong Meng Lee; Jia Zhen Zheng; Ravi Sundaresan; Kin Leong Pey
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Paper Abstract

Advanced Ti-Salicide schemes using Si implantation either before or after Ti deposition adversely affected transistor performance through lowering of the device drivability. Device impact was sen in increase of the pMOS series resistance with increasing per-amorphization implant Si implant energy. Likewise, the amount of amorphization and silicidation due to different as-deposited Ti thickness for the implant through metal scheme affected most adversely for the pMOS. This degradation is attributed to the implantation and silicidation induced generation of vacancies and interstitials, resulting in the de-activation and subsequent re-distribution of dopants around the transistor LDD and source/drain regions. Results were shown to conform with TRIM simulation of Si implantation profiles.

Paper Details

Date Published: 1 September 1999
PDF: 7 pages
Proc. SPIE 3881, Microelectronic Device Technology III, (1 September 1999); doi: 10.1117/12.360546
Show Author Affiliations
Eng-Hua Lim, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Soh Yun Siah, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Chong Wee Lim, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Yong Meng Lee, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Jia Zhen Zheng, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Ravi Sundaresan, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Kin Leong Pey, National Univ. of Singapore (Singapore)


Published in SPIE Proceedings Vol. 3881:
Microelectronic Device Technology III
David Burnett; Toshiaki Tsuchiya, Editor(s)

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