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Proceedings Paper

Improved p-ch MOS transistor performance with an arsenic supersteep retrograde channel profile
Author(s): James F. Buller; Jon Cheek; Dirk Wristers; Daniel Kadoch; Michael Duane
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Paper Abstract

The benefits of super steep retrograde channel profiles on MOS transistor performance as reported in the literature have been inconsistent. This inconsistency is in part due to the sensitivity of the performance benefit to the process parameters and integration of the retrograde channel profile. As exhaustive study that integrated and optimized a p-ch arsenic retrograde channel profile transistor into a high performance sub 0.18micrometers transistor CMOS microprocessor process was performed. It was found that the dose and energy of the retrograde channel implant significantly affected the performance improvement obtained. A higher SSRC implant dose, or lower implant energy resulted in higher drive current for a given off current relative to a conventional channel profile control transistor. In addition, the improvement in the transistor linear current was even more significant. At IDOFF equals 1nA, the IDS and IDLIN improvement was approximately 10 percent and 16 percent, respectively. Improvement in transistor drive current also increased at higher drive current. The saturated threshold voltage and Drain Induced Barrier Lowering roll-off with effective channel length were superior for the retrograde channel profile versus the conventional channel profile transistor. Gate oxide reliability with the arsenic doping was also evaluated using Voltage Ramped Dielectric Breakdown (VRDB). It was found that the p-ch gate oxide capacitor VRDB failure rate with the arsenic retrograde channel doping profile was as good or better compared with the conventional phosphorous doped channel profile.

Paper Details

Date Published: 1 September 1999
PDF: 7 pages
Proc. SPIE 3881, Microelectronic Device Technology III, (1 September 1999); doi: 10.1117/12.360544
Show Author Affiliations
James F. Buller, Advanced Micro Devices, Inc. (United States)
Jon Cheek, Advanced Micro Devices, Inc. (United States)
Dirk Wristers, Advanced Micro Devices, Inc. (United States)
Daniel Kadoch, Advanced Micro Devices, Inc. (United States)
Michael Duane, Advanced Micro Devices, Inc. (United States)

Published in SPIE Proceedings Vol. 3881:
Microelectronic Device Technology III
David Burnett; Toshiaki Tsuchiya, Editor(s)

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