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Proceedings Paper

Optimal design and implementation of parallel VLSI circuits dedicated to image matching
Author(s): Edwige E. Pissaloux; Francois Le Coat; Patrick J. Bonnin; Andre Tissot; Francois Durbin
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Paper Abstract

This paper addresses the problem of architecture optimization, when implementing an image matching primitive in reconfigurable circuits. Circuit spatial organization is optimized in terms of processing time, and circuit volume, in order to suit well for real time on board applications. This optimized adaptive spatial and scalable organization of the (mu) PD circuit dedicated to image matching reduces by one order the spatial and temporal performance, without altering the quality of matching. The (mu) PD circuit has been validated with the minimal 22 elementary cells architecture with Xilinx 4010 XL circuit working at 12 MHz and occupying 92 percent of the circuit CLB. It performs the pyramidal 256 X 256 image matching in less than 1 s.

Paper Details

Date Published: 26 August 1999
PDF: 9 pages
Proc. SPIE 3837, Intelligent Robots and Computer Vision XVIII: Algorithms, Techniques, and Active Vision, (26 August 1999); doi: 10.1117/12.360318
Show Author Affiliations
Edwige E. Pissaloux, Univ. de Rouen and Lab. de Robotique de Paris (France)
Francois Le Coat, Institut d'Electronique Fondamentale (France)
Patrick J. Bonnin, Lab. de Robotique de Paris (France)
Andre Tissot, CEA (France)
Francois Durbin, CEA (France)


Published in SPIE Proceedings Vol. 3837:
Intelligent Robots and Computer Vision XVIII: Algorithms, Techniques, and Active Vision
David P. Casasent, Editor(s)

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