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Proceedings Paper

Algorithm-agile cryptographic coprocessor based on FPGAs
Author(s): Christof Paar; Brendon Richard Chetwynd; Thomas J. Connor; Sheng Yung Deng; Stephen J. Marchant
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Paper Abstract

This contribution describes the design and implementation of an algorithm-agile cryptographic co-processor board. The core of the board is an FPGA which can be dynamically configured with a variety of block ciphers. The FPGA is capable of encrypting data at high speed through an ISA bus interface. The board contains a RAM with a collection of FPGA configuration files. In addition, the algorithms can be added or deleted during operation. The co-processor board also contains other reconfigurable logic and a microprocessor for control functions, and high-speed FIFOs for data storage. We report about the general design, our experiences with this proof-of-concept implementation, and recommendations for future work.

Paper Details

Date Published: 26 August 1999
PDF: 6 pages
Proc. SPIE 3844, Reconfigurable Technology: FPGAs for Computing and Applications, (26 August 1999);
Show Author Affiliations
Christof Paar, Worcester Polytechnic Institute (United States)
Brendon Richard Chetwynd, Worcester Polytechnic Institute (United States)
Thomas J. Connor, Worcester Polytechnic Institute (United States)
Sheng Yung Deng, Worcester Polytechnic Institute (United States)
Stephen J. Marchant, Worcester Polytechnic Institute (United States)

Published in SPIE Proceedings Vol. 3844:
Reconfigurable Technology: FPGAs for Computing and Applications
John Schewel; Peter M. Athanas; Steven A. Guccione; Stefan Ludwig; John T. McHenry, Editor(s)

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