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Proceedings Paper

Adaptive 2D feature detection using dynamic reconfiguration
Author(s): Stephen M. Charlwood; Philip B. James-Roxby; Richard L. Walke
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Paper Abstract

The ability of rapidly reconfigure the gate-level logic of SRAM-based FPGAs at run-time allows algorithm implementations to be both adaptive and highly application- specific. In this way, adaptive algorithms can be implemented in hardware, and deliver high performance with a flexibility not normally associated with an application- specific solution. This paper describes the static implementation and operation of an adaptive image- enhancement algorithm called SUSAN on a Xilinx XC4085XL, demonstrating order-of-magnitude performance improvements over optimized software running on high-end general-purpose processors, and discusses the implementation of adaptive solutions in both hardware and software. The effective use of dynamic reconfiguration for run-time reconfigurable systems based on XC4000-series devices is examined, along with the use of the JBits API for implementing FPGA-based adaptive signal processing algorithms. Both the performance and suitability of XC4000-series devices for adaptive processing are shown to be critically dependent on device capacity.

Paper Details

Date Published: 26 August 1999
PDF: 12 pages
Proc. SPIE 3844, Reconfigurable Technology: FPGAs for Computing and Applications, (26 August 1999); doi: 10.1117/12.359533
Show Author Affiliations
Stephen M. Charlwood, Univ. of Birmingham (United Kingdom)
Philip B. James-Roxby, Univ. of Birmingham (United States)
Richard L. Walke, Defence Evaluation and Research Agency (United Kingdom)

Published in SPIE Proceedings Vol. 3844:
Reconfigurable Technology: FPGAs for Computing and Applications
John Schewel; Peter M. Athanas; Steven A. Guccione; Stefan Ludwig; John T. McHenry, Editor(s)

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