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Proceedings Paper

Optical proximity correction considering process latitude
Author(s): Akio Misaka; Shinji Odanaka
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Paper Abstract

A two-step OPC approach, that consists of a cell level OPC and a chip level OPC, is proposed. The cell level OPC plays an important role on generating the layout design rules of gate patterns at the initial phase of technology development. The chip level OPC is dedicated to CD adjustment. The Cell level OPC includes the OPC patten generator and the verification part on the basis of a 3D aerial simulation. The effect of the OPC pattern is estimated, calculating the process windows. Cell layout patterns and OPC patterns are generated so as to maximize the process windows. The cell level OPC allows us to remove the error that breaks out in the cell size reduction process.

Paper Details

Date Published: 26 July 1999
PDF: 11 pages
Proc. SPIE 3679, Optical Microlithography XII, (26 July 1999); doi: 10.1117/12.354379
Show Author Affiliations
Akio Misaka, Matsushita Electronics Corp. (Japan)
Shinji Odanaka, Matsushita Electronics Corp. (Japan)

Published in SPIE Proceedings Vol. 3679:
Optical Microlithography XII
Luc Van den Hove, Editor(s)

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