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Proceedings Paper

Digital-readout CMOS design for capacitive sensors using on-chip variable sense capacitor arrays
Author(s): Ashok Srivastava; Hanson Yong; Daniel Wildhaber; Mohammed Hasan; Vishnupriya Gongalreddy; Jing Wang; Pratul K. Ajmera; Farzad Pouralborz
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Paper Abstract

A digital readout design in CMOS technology is described for monolithic integration with microelectromechanical capacitive sensors using on-chip variable sense capacitor arrays with resolutions of 2.5 fF, 10 fF and 40 fF, respectively. The designed circuit produces a 4-bit digital readout proportional to the capacitive difference between the sense and the reference capacitors. The CMOS digital readout is compatible with +/- 1.5 V operation for low power consumption, uses a +1.5 V reference voltage with a switching speed of approximately 100 kHz. The digital readout design presented here is quite general and can be used in a wide variety of analog microsensors on the chip.

Paper Details

Date Published: 20 July 1999
PDF: 11 pages
Proc. SPIE 3673, Smart Structures and Materials 1999: Smart Electronics and MEMS, (20 July 1999); doi: 10.1117/12.354284
Show Author Affiliations
Ashok Srivastava, Louisiana State Univ. (United States)
Hanson Yong, Louisiana State Univ. (United States)
Daniel Wildhaber, Louisiana State Univ. (United States)
Mohammed Hasan, Louisiana State Univ. (United States)
Vishnupriya Gongalreddy, Louisiana State Univ. (United States)
Jing Wang, Louisiana State Univ. (United States)
Pratul K. Ajmera, Louisiana State Univ. (United States)
Farzad Pouralborz, Louisiana State Univ. (United States)


Published in SPIE Proceedings Vol. 3673:
Smart Structures and Materials 1999: Smart Electronics and MEMS
Vijay K. Varadan, Editor(s)

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