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Proceedings Paper

Methodology for yield enhancement based on the analysis of defects at the lithographic step
Author(s): Manda Kulkarni; Andrew Skumanich
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Paper Abstract

Defect reduction for both process development and process maintenance requires capturing the defects, evaluating the impact of these defects, and identifying and eliminating the key defects. It is necessary to understand the nature of the various lithography defects and their potential impact since only certain effects may have a significant impact on yield. A WF700 series patterned wafer inspection tool was utilized to capture a wide range of defects at the lithography step, and track and progression of these defects through processing to the etch and strip step. The lithography defects were correlated with the final step effects. For instance, specific lithography defects were determined to cause metal bridging defects and un-cleared contacts. By tracking the defects, and by establishing the source of the lithography defects, it was possible to eliminate the final step defects. Some of the lithography defects captured were too subtle for optical imaging and required a SEM for analysis. Further, the unique ability of the WF700 series to segregate defects during the inspection with no loss in throughput allowed for a significant reduction in analysis time and faster defect sourcing. A methodology is presented for defect reduction and yield enhancement based on inspection at the lithographic step.

Paper Details

Date Published: 14 June 1999
PDF: 12 pages
Proc. SPIE 3677, Metrology, Inspection, and Process Control for Microlithography XIII, (14 June 1999); doi: 10.1117/12.350837
Show Author Affiliations
Manda Kulkarni, VLSI Technology, Inc. (United States)
Andrew Skumanich, Applied Materials (United States)

Published in SPIE Proceedings Vol. 3677:
Metrology, Inspection, and Process Control for Microlithography XIII
Bhanwar Singh, Editor(s)

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