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Proceedings Paper

CD error budget analysis for 0.18-um inlaid trench lithography
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Paper Abstract

Lithographic patterning of small inlaid trenches is becoming increasingly important for leading edge semiconductor manufacturing. Correct patterning of these small inlaid features is made difficult by inherent difficulties in darkfield pattern imaging, large substrate reflectivity variations, large sensitivity to reticle CD variations and stringent requirements for the photoresist etch mask. Additionally, successful process optimization requires accurate knowledge of the lithographic errors affecting CD control. We present her a CD control error budget analysis for 0.18 um inlaid trench lithography using 0.6 NA 248 nm exposure tools and high resolution chemically amplified resist. Experiment and tuned simulation are used to translate tool, process and reticle variations into wafer CD variations. Results of across-field and across-wafer error analysis for different process choices are presented as are experimental verifications of their accuracy. Conclusions presented include the significant impact of stepper best- focus determination for across-field CD variation and the considerable overall CD control improvements observed with thin photoresist and strong phase shift processes.

Paper Details

Date Published: 14 June 1999
PDF: 11 pages
Proc. SPIE 3677, Metrology, Inspection, and Process Control for Microlithography XIII, (14 June 1999); doi: 10.1117/12.350827
Show Author Affiliations
Sergei V. Postnikov, Univ. of Texas/Austin (United States)
John L. Sturtevant, Motorola (United States)
Kevin D. Lucas, Motorola (Belgium)
Chong-Cheng Fu, Motorola (United States)

Published in SPIE Proceedings Vol. 3677:
Metrology, Inspection, and Process Control for Microlithography XIII
Bhanwar Singh, Editor(s)

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