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Proceedings Paper

Bilayer silylation process for 193-nm lithography
Author(s): Isao Satou; Koichi Kuhara; Masayuki Endo; Hiroaki Morimoto
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Paper Abstract

Top surface imaging (TSI) techniques have been studied in order to enlarge the process window for fine pattern fabrication. We have been evaluating the silylation process for 193 nm lithography as one of the TSI techniques, and in this paper, we would like to focus on the effect of the silylation resist thickness of the process window. We found that a very thin silylation resists was effective in widening the fine pattern fabricating margin, and we tried to use a thin silylation resist as the top layer of the bi- layer resist system for practical applications. In order to fully realize the ability of this bi-layer silylation process, we optimized the dry-development conditions and resist structures before evaluation of the lithographic performance. A negative tone resist was used in our bi-layer silylation process, and positive tone patterns were generated after the dry-development. In this process, the depth of the silylated area was controlled, and the excess swelling caused by too many silylation reactions was restricted. Moreover, the profile of the silylated area was formed into an almost rectangular shape which was good and appropriate for precise critical dimension control. The process window was significantly enlarged, and the 0.11 micrometers L/S patterns were successfully fabricated without using any resolution enhancement techniques. We confirmed that the bi-layer silylation process is one of the best approaches to improve the lithographic performance of the silylation process.

Paper Details

Date Published: 11 June 1999
PDF: 11 pages
Proc. SPIE 3678, Advances in Resist Technology and Processing XVI, (11 June 1999); doi: 10.1117/12.350208
Show Author Affiliations
Isao Satou, Semiconductor Leading Edge Technologies, Inc. (Japan)
Koichi Kuhara, Semiconductor Leading Edge Technologies, Inc. (Japan)
Masayuki Endo, Semiconductor Leading Edge Technologies, Inc. (Japan)
Hiroaki Morimoto, Semiconductor Leading Edge Technologies, Inc. (Japan)

Published in SPIE Proceedings Vol. 3678:
Advances in Resist Technology and Processing XVI
Will Conley, Editor(s)

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