
Proceedings Paper
Technique of analog integrated circuit yield analysisFormat | Member Price | Non-Member Price |
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Paper Abstract
The technique of analog integrated circuits statistical analysis is suggested. This technique enables to determine the interrelation between integrated circuit yield on the one hand and the dimensions of elements on the other hand. The idea is based on the common use of experimental statistical analysis and statistical modeling and on the introduction of the concept of the integrated circuit intermediate parameters. The results of statistical analysis of two analog integrated circuits has been cited as an example of suggested technique. They show that there exist optimal dimensions of integrated circuits elements by yield maximum criteria and the values of optimal dimensions of elements depend on process technology level and the requirements for integrated circuits output parameters.
Paper Details
Date Published: 27 April 1999
PDF: 10 pages
Proc. SPIE 3743, In-Line Characterization, Yield Reliability, and Failure Analyses in Microelectronic Manufacturing, (27 April 1999); doi: 10.1117/12.346931
Published in SPIE Proceedings Vol. 3743:
In-Line Characterization, Yield Reliability, and Failure Analyses in Microelectronic Manufacturing
Kostas Amberiadis; Gudrun Kissinger; Katsuya Okumura; Seshu Pabbisetty; Larg H. Weiland, Editor(s)
PDF: 10 pages
Proc. SPIE 3743, In-Line Characterization, Yield Reliability, and Failure Analyses in Microelectronic Manufacturing, (27 April 1999); doi: 10.1117/12.346931
Show Author Affiliations
Algirdas Baskys, Semiconductor Physics Institute (Lithuania)
Vitold Gobis, Semiconductor Physics Institute (Lithuania)
Published in SPIE Proceedings Vol. 3743:
In-Line Characterization, Yield Reliability, and Failure Analyses in Microelectronic Manufacturing
Kostas Amberiadis; Gudrun Kissinger; Katsuya Okumura; Seshu Pabbisetty; Larg H. Weiland, Editor(s)
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