Share Email Print

Proceedings Paper

Comparative assessment of yield learning tools using information theory
Author(s): Charles Weber; Vijay Sankaran; Kenneth W. Tobin Jr.; Gary Scher
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

A model based on information theory, which allows yield managers to choose the optimal strategies for yield management in microelectronic manufacturing, is presented. The data reduction rate per experimentation cycle and data reduction rate per unit time serve as benchmarking metrics for yield learning. These newly defined metrics enable managers to make objective comparisons of apparently unrelated technologies. Four yield analysis tools -- electrical testing, automatic defect classification, spatial signature analysis and wafer position analysis -- are examined in detail to suggest an optimal yield management strategy for both the R and D and volume production environments.

Paper Details

Date Published: 27 April 1999
PDF: 8 pages
Proc. SPIE 3743, In-Line Characterization, Yield Reliability, and Failure Analyses in Microelectronic Manufacturing, (27 April 1999); doi: 10.1117/12.346930
Show Author Affiliations
Charles Weber, Massachusetts Institute of Technology (United States)
Vijay Sankaran, SEMATECH (United States)
Kenneth W. Tobin Jr., Oak Ridge National Lab. (United States)
Gary Scher, Sleuthworks, Inc. (United States)

Published in SPIE Proceedings Vol. 3743:
In-Line Characterization, Yield Reliability, and Failure Analyses in Microelectronic Manufacturing
Kostas Amberiadis; Gudrun Kissinger; Katsuya Okumura; Seshu Pabbisetty; Larg H. Weiland, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?