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Proceedings Paper

Utilization of optical metrology as an in-line characterization technique for process performance improvement and yield enhancement of dielectric and metal CMP in IC manufacturing
Author(s): Albert H. Liu; Randy Solis; John H. Givens
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Paper Abstract

Optical metrology equipment has been widely used as the process qualification gauge for chemical mechanical polish and planarization (CMP) processes. However, most of the effort has concentrated on blanket-film wafers. Recent advancements in the optical metrology equipment have provided the ability to monitor both dielectric and metal CMP processes on production wafers in order to provide an in-line, real time characterization technique for performance and yield enhancement. This paper describes a methodology of using circuit features in the die as measurement sites for revealing the fundamentals of CMP. By measuring the oxide thickness on top of one or several similar circuit features and repeating the measurements through out the wafer, the oxide removal profile during CMP process can be easy plotted against the measurement sites. By carefully selecting the measurement feature, the polish removal profile at the edge of the wafers can be correlated with the results form similar test on blanket-film wafers. The results of using this technique to characterize existing CMP processes, identify the product-yield limiting factors in CMP processes, verify the improvement of a new CMP process and monitor the process variations for both dielectric and metal CMP processes have been discussed in detail. With the assistance of this measurement technique the correlation between the polish rate profiles of blanket pilot test wafers and the oxide loss profiles for production wafers can be easily identified. And, as another quantifiable result, the learning curve for process development and yield improvement can be significantly reduced.

Paper Details

Date Published: 27 April 1999
PDF: 10 pages
Proc. SPIE 3743, In-Line Characterization, Yield Reliability, and Failure Analyses in Microelectronic Manufacturing, (27 April 1999); doi: 10.1117/12.346903
Show Author Affiliations
Albert H. Liu, VLSI Technology, Inc. (United States)
Randy Solis, VLSI Technology, Inc. (United States)
John H. Givens, VLSI Technology, Inc. (United States)

Published in SPIE Proceedings Vol. 3743:
In-Line Characterization, Yield Reliability, and Failure Analyses in Microelectronic Manufacturing
Kostas Amberiadis; Gudrun Kissinger; Katsuya Okumura; Seshu Pabbisetty; Larg H. Weiland, Editor(s)

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