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Proceedings Paper

Process window overlap for posts and lines and spaces: optimization by resist type, optical settings, and mask bias
Author(s): Michael T. Reilly; Karen Kvam; Jentry Willie
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Paper Abstract

Lines and spaces with posts are a typical combination of feature types for metal layer applications. A common process window for these is difficult to achieve, especially for equally sized features on the wafer. Foremost in attaining one is minimizing the differences in the dose to size of the feature. Many methods have been studied to maximize overlapping process windows of different features. Direct feature biasing, assist features and running NA and sigma are all methods that can be applied to maximize overlap. In this work, two different feature types, isolated and dense lines and posts, are examined. It is shown, through simulation and experimentation, how the overlapping process window (OLPW) of these features can be optimized. PROLITH software will be used to simulate OLPW with the latest resist models. This is examined experimentally, using an ASM 5500/300 DUV stepper with variable NA and partial coherence, for 250nm dense and isolated lines and 250 nm posts at optimal illumination settings which are determined by PROLITH. The improvements in OLPW due to resist type, e.g.; positive tine UV6 and negative tone UVN30, combined with optimal illumination coherence and mask bias, are shown. Mask feature bias is examined for the amounts that produce a common process at each of three partial coherence settings. Also given are the trends for isolated to dense and line to post proximity bias and the comparison of these to simulation.

Paper Details

Date Published: 28 April 1999
PDF: 6 pages
Proc. SPIE 3741, Lithography for Semiconductor Manufacturing, (28 April 1999); doi: 10.1117/12.346898
Show Author Affiliations
Michael T. Reilly, Shipley Co., LLC (United States)
Karen Kvam, Shipley Co., LLC (United States)
Jentry Willie, Northeastern Univ. (United States)

Published in SPIE Proceedings Vol. 3741:
Lithography for Semiconductor Manufacturing
Chris A. Mack; Tom Stevenson, Editor(s)

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