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Proceedings Paper

Chip-level three-dimensional assembling of microsystems
Author(s): Hiroshi Toshiyoshi; Yoshio Mita; Minoru Ogawa; Hiroyuki Fujita
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Paper Abstract

We propose a new method of assembling 3D microsystems by means of chip level electrical interconnection. Silicon dies are flip-chipped out of a silicon wafer by using ICP-RIE instead of a dicing saw. Fringes of the chips are patterned into pin-shapes so that they can be vertically inserted into the micro motherboard for electrical and physical connection. The pins are coated with Cr-Au, and the contact pads are electroplated with Cu for low contact resistance. the pins are tapered in width, and assembling was easily done by manual positing under the optical binocular microscope. This technique is a break through to the hybrid integration of various kinds of micro chips independent of materials or fabrication compatibility.

Paper Details

Date Published: 10 March 1999
PDF: 8 pages
Proc. SPIE 3680, Design, Test, and Microfabrication of MEMS and MOEMS, (10 March 1999); doi: 10.1117/12.341260
Show Author Affiliations
Hiroshi Toshiyoshi, Univ. of Tokyo (Japan)
Yoshio Mita, Univ. of Tokyo (Japan)
Minoru Ogawa, Toshiba TEC Co. (Japan)
Hiroyuki Fujita, Univ. of Tokyo (Japan)

Published in SPIE Proceedings Vol. 3680:
Design, Test, and Microfabrication of MEMS and MOEMS
Bernard Courtois; Wolfgang Ehrfeld; Selden B. Crary; Wolfgang Ehrfeld; Hiroyuki Fujita; Jean Michel Karam; Karen W. Markus, Editor(s)

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