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Proceedings Paper

Architectural issues in VLIW video signal processors
Author(s): Zhao Wu; Wayne H. Wolf
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Paper Abstract

As digital video becomes more prevalent, video signal processors (VSPs) emerge as a solution to accelerate computational-intensive multimedia applications. While dedicated VSPs are available for MPEG CODECs, the need for greater functionality and time-to-market pressures will push the video industry towards programmable VSPs. Combining a high degree of parallelism with the efficiency of statistically scheduled instructions, very long instruction word micro-architecture is becoming very popular and widely adopted. In this paper, we provide an overview of problems involved in VSP design, including hierarchical architectural paradigm, register and memory sizing, streaming computation, and so on. Analyses and solutions are also presented in addition to problem formulation. Understanding these problems well would help us realize architectural tradeoffs and pinpoint bottleneck in different stages of design sophistication.

Paper Details

Date Published: 22 January 1999
PDF: 10 pages
Proc. SPIE 3528, Multimedia Systems and Applications, (22 January 1999); doi: 10.1117/12.337417
Show Author Affiliations
Zhao Wu, Princeton Univ. (United States)
Wayne H. Wolf, Princeton Univ. (United States)

Published in SPIE Proceedings Vol. 3528:
Multimedia Systems and Applications
Andrew G. Tescher; Bhaskaran Vasudev; V. Michael Bove Jr.; Barbara Derryberry, Editor(s)

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