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Proceedings Paper

MPEG-4 video communication processor architecture
Author(s): Kathy Moseler; Robert Chen; Sami Levi
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Paper Abstract

Acceptable video quality in standards-based video communication requires the use of hardware acceleration. Traditional approaches to this in recent years have been a hardwired approach, in which video compression algorithms cannot be changed, and a fully programmable approach, in which a single VLIW processor is programmed in a high-level language (such as `C') or assembly. The drawback of the hardwired approach has been inflexibility and difficulty of adding performance enhancements since new silicon is needed to make improvements. The drawback of the fully programmable approach is the difficulty in developing software and tools for the processor. This has the new result of lengthening the overall design cycle time. A new approach, described in this paper, uses multiple VLIW processing elements, some of which are pipelined, that have reprogrammable microcode. This allows particular algorithm classes, such as DCT/IDCT, motion compensation or motion estimation, to be reprogrammed to improve performance without changing the silicon. First, overviews of a new MPEG4 Video Communication system architecture and its hardware synthesis process are given. Then, two methods for reprogramming the microcode for the motion estimator are discussed and compared. Finally, comparisons of our system architecture to the traditional hardwired architecture and the fully programmable architecture are given.

Paper Details

Date Published: 21 December 1998
PDF: 11 pages
Proc. SPIE 3655, Media Processors 1999, (21 December 1998); doi: 10.1117/12.334754
Show Author Affiliations
Kathy Moseler, Motorola (United States)
Robert Chen, Motorola (United States)
Sami Levi, Motorola (United States)

Published in SPIE Proceedings Vol. 3655:
Media Processors 1999
Sethuraman Panchanathan; Subramania I. Sudharsanan; V. Michael Bove Jr., Editor(s)

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