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Proceedings Paper

Development of a multi-FPGA netlist partitioner and a general-purpose graph partitioning system
Author(s): Preeti Gowaikar; Millind Sohoni; M. Chandramouri; Sachin Patkar
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Paper Abstract

We describe here a general purpose graph partitioning system, especially suitable for VLSI applications. The partitioner has at its core a spectral based graph partitioner. In our strategy, the input netlist is first coarsened into a smaller netlist and the core spectral partitioner then proceeds to partition this coarsened netlist. This coarse partition is then lifted to a partition of the original netlist. The coarsener is fairly subtle and uses the theory of submodular functions, and of matchings. We also highlight some of our results.

Paper Details

Date Published: 1 September 1998
PDF: 9 pages
Proc. SPIE 3412, Photomask and X-Ray Mask Technology V, (1 September 1998); doi: 10.1117/12.328816
Show Author Affiliations
Preeti Gowaikar, Indian Institute of Technology (India)
Millind Sohoni, Indian Institute of Technology (India)
M. Chandramouri, Indian Institute of Technology (India)
Sachin Patkar, Indian Institute of Technology (India)

Published in SPIE Proceedings Vol. 3412:
Photomask and X-Ray Mask Technology V
Naoaki Aizaki, Editor(s)

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