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Proceedings Paper

Yield issues with local interconnect
Author(s): Neil Bryan Henis; Scott Bolton; Ruben Montez; James Legg; Sung Kim; Quong Vuong
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Paper Abstract

We report here on process integration issues in the interconnect module of advanced microprocessor. We show how stresses in certain layers can affect yield and result in novel failure mechanisms in other layers. The paper will follow the history of a yield crash from beginning to end. We show how the problem was isolated, how yields were raised once the issues were fixed, and how an understanding of the issues involved can allow us to construct a more robust process from the beginning, therefore minimizing the possibility of such problems occurring in the first pace. The particular work here involves interactions of TiN with TEOS layers, and shows how local interconnect shorting can be caused by interactions between all of these layers. Stress effects in the as deposited TEOS films, although not obvious, can play a large role in determining whether or not problems occur. We also will examine how supposedly identical tools, or even two chambers within one tool can produce dramatically different end results in terms of film properties.

Paper Details

Date Published: 28 August 1998
PDF: 7 pages
Proc. SPIE 3510, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV, (28 August 1998); doi: 10.1117/12.324375
Show Author Affiliations
Neil Bryan Henis, Motorola (United States)
Scott Bolton, Motorola (United States)
Ruben Montez, Motorola (United States)
James Legg, Motorola (United States)
Sung Kim, Samsung Inc. (United States)
Quong Vuong, Samsung Inc. (United States)

Published in SPIE Proceedings Vol. 3510:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV
Sharad Prasad; Hans-Dieter Hartmann; Tohru Tsujide, Editor(s)

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