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Proceedings Paper

Influence of floating gate tungsten polycide deposition technique on EEPROM electrical characteristics
Author(s): Karine Ogier-Monnier; Philippe Boivin; Olivier Bonnaud
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Paper Abstract

In CMOS technology, polycide material is often used to from the gate electrode. This bilayer composed of tungsten silicide layer and of doped polycrystalline layer, preserves a good silicon/oxide interface and has low resistivity. Different processes can be used to deposit the polycide. The first process which is conventional corresponds to a polysilicon deposition in furnace followed by a POCl3 doping technique. Then the tungsten silicide is deposited. The second process involved a single wafer reactor. It allows to deposit the in-situ doped polycrystalline layer an the WSix layer in the same equipment. The aim of this work is to study the impact of these tow processes on the electrical behavior of the EEPROM, more especially on the endurance and on data retention. After the presentation of the fabrication processes, physical and electrical characteristics of both types of devices are discussed. The conventional gate degrades more the cycling performance of the memory cell.

Paper Details

Date Published: 3 September 1998
PDF: 6 pages
Proc. SPIE 3507, Process, Equipment, and Materials Control in Integrated Circuit Manufacturing IV, (3 September 1998); doi: 10.1117/12.324339
Show Author Affiliations
Karine Ogier-Monnier, SGS-Thomson Microelectronics (France)
Univ. de Rennes I (France)
Philippe Boivin, SGS-Thomson Microelectronics (France)
Olivier Bonnaud, Univ. de Rennes I (France)

Published in SPIE Proceedings Vol. 3507:
Process, Equipment, and Materials Control in Integrated Circuit Manufacturing IV
Anthony J. Toprac; Kim Dang, Editor(s)

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