Share Email Print

Proceedings Paper

FRAM technologies compatible with 0.5-um CMOS logics
Author(s): Yuji Furumura; Tatsuya Yamazaki; Mitsuhiro Nakamura; Ken-ichi Inoue; Hisashi Miyazawa; Naoya Sashida; Rei Satomi; Yoshikazu Katoh; Souichirou Ozawa; Kazuaki Takai; Hideyuki Noshiro; Rika Shinohara; Yoshiroh Obata; Andrew Kerry; Kouji Tani; Sinji Nakashima; Tetsuya Nakajima; Masahiko Imai; Tohru Takesima; Toshiyuki Teramoto; Chikai Ohono; Moritaka Nakamura; Takayuki Murakami
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

We developed FRAM (FRAM is a registered trademark of Ramtron International Corporation that stands for FeRAM) technologies that are fully compatible with half-micron CMOS logic's. The technologies achieve 1T/1C FRAM cell 12.5 micrometer2 in a size and 68k-FRAM embedded 8bit-MCU. The CMOS transistors work at 5V for a cell operation and 3V for a logic operation. We did not use a COB to employ a present CMOS processing, and used the local interconnect to reduce a chip size. We used the W plug to contact to deep diffusion layers through high-aspect contact holes. The CMP planarization was used to relax PZT deposition and Pt etching. To prevent the process degradation of PZT, we used single Al wiring with SOG as an interlayer dielectric. The cover dielectric was formed with plasma TEOS- CVD without SiN to prevent the process degradation at this case. The SiN cover will be indispensable in real products. These technologies achieved a cell size 6.95 X 1.8 equals 12.5 (micrometer2) for 1T/1C and 4.2 X 6.5 equals 27.3(micrometer2) for 2T/2C that are the smallest cell size in FRAM's that do not use a COB structure and a poly-plug as a storage.

Paper Details

Date Published: 4 September 1998
PDF: 9 pages
Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); doi: 10.1117/12.323989
Show Author Affiliations
Yuji Furumura, Fujitsu Ltd. (Japan)
Tatsuya Yamazaki, Fujitsu Ltd. (Japan)
Mitsuhiro Nakamura, Fujitsu Ltd. (Japan)
Ken-ichi Inoue, Fujitsu Ltd. (Japan)
Hisashi Miyazawa, Fujitsu Ltd. (Japan)
Naoya Sashida, Fujitsu Ltd. (Japan)
Rei Satomi, Fujitsu Ltd. (Japan)
Yoshikazu Katoh, Fujitsu Ltd. (Japan)
Souichirou Ozawa, Fujitsu Ltd. (Japan)
Kazuaki Takai, Fujitsu Ltd. (Japan)
Hideyuki Noshiro, Fujitsu Ltd. (Japan)
Rika Shinohara, Fujitsu Ltd. (Japan)
Yoshiroh Obata, Fujitsu Ltd. (Japan)
Andrew Kerry, Fujitsu Ltd. (Japan)
Kouji Tani, Fujitsu Ltd. (Japan)
Sinji Nakashima, Fujitsu Ltd. (Japan)
Tetsuya Nakajima, Fujitsu Ltd. (Japan)
Masahiko Imai, Fujitsu Ltd. (Japan)
Tohru Takesima, Fujitsu Ltd. (Japan)
Toshiyuki Teramoto, Fujitsu Ltd. (Japan)
Chikai Ohono, Fujitsu Ltd. (Japan)
Moritaka Nakamura, Fujitsu Ltd. (Japan)
Takayuki Murakami, Fujitsu Ltd. (Japan)

Published in SPIE Proceedings Vol. 3506:
Microelectronic Device Technology II
David Burnett; Dirk Wristers; Toshiaki Tsuchiya, Editor(s)

© SPIE. Terms of Use
Back to Top