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Proceedings Paper

Evaluation of Mo-doped Ti salicide process for sub-0.18-um CMOS
Author(s): Chih-Ping Chao; Jorge A. Kittl; Qi-Zhong Hong; Wei-Tsun Shiau; Mark Rodder; Ih-Chin Chen
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Paper Abstract

For scaled CMOS technology with gate length down to sub-0.25 micrometer, the conventional Ti salicide suffers from high polygate sheet resistance (Rsheet) due to difficulty in the low resistivity C54 TiSi2 phase transition. To improve the sub 0.25 micrometer TiSi2 Rsheet, pre-amorphization implant (PAI) was added to achieve low Rsheet down to approximately 0.1 micrometer gate length, and PAI based TiSi2 has been the base-line salicide process for current 0.25 micrometer CMOS technology. However, various studies on sub 0.18 micrometer devices have shown that PAI process tends to induce additional S/D dopant diffusion and results in the series resistance (RSD) increase and drive current degradation, especially for pMOS transistors. On the other hand, Mo implant was found effective in enhancing the C54 TiSi2 formation for narrow lines and has the potential to realize a simplified TiSi2 process with one single thermal step. However, the Mo based Ti salicide is still relatively new to date, and a complete CMOS study is helpful in identifying the trade-offs for such a process. In this work, we present a detailed CMOS evaluation of Mo doped TiSi2 process. Two different Mo based processes are studied: (1) Mo implant into gate before gate pattern (Mo-A case). In this case, the source/drain (S/D) diffusion regions have minimal Mo doping. (2) Mo implant into gate and S/D regions right before the S/D anneal (Mo-B case). For both Mo-A and Mo-B processes, we also studied the effect of Mo doses and the difference between the conventional 2-step rapid thermal process (RTP), low-temperature formation plus Ti strip plus high-temperature anneal, and the 1-step RTP process, namely low-T formation plus Ti stripe, where the high-T anneal is skipped. The results of the Mo processes are compared with three other reference salicide processes: conventional TiSi2 without PAI (Conv.), TiSi2 with Ge or As PAI and the emerging CoSi2 technology. The following CMOS care-abouts are evaluated for the various salicide processes: (1) polysilicon and diffusion region Rsheet, (2) various bridging mechanisms, (3) diode leakages: bottom junction, trench edge and gate edge leakage currents, (4) drive current and RSD, and (5) charge to breakdown (QBD).

Paper Details

Date Published: 4 September 1998
PDF: 11 pages
Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); doi: 10.1117/12.323958
Show Author Affiliations
Chih-Ping Chao, Texas Instruments Inc. (United States)
Jorge A. Kittl, Texas Instruments Inc. (United States)
Qi-Zhong Hong, Texas Instruments Inc. (United States)
Wei-Tsun Shiau, Texas Instruments Inc. (United States)
Mark Rodder, Texas Instruments Inc. (United States)
Ih-Chin Chen, Texas Instruments Inc. (United States)

Published in SPIE Proceedings Vol. 3506:
Microelectronic Device Technology II
David Burnett; Dirk Wristers; Toshiaki Tsuchiya, Editor(s)

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