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Proceedings Paper

Monolithic 2.5-Gb/s clock and data recovery circuit based on silicon bipolar technology
Author(s): Andrea Pallotta; Francesco Centurelli; Francesco Loriga; Alessandro Trifiletti
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Paper Abstract

A monolithic Clock and Data Recovery (CDR) circuit for SDH STM-16 (2.5 Gb/s) digital receivers has been designed and fabricated using Maxim GST-2 27 GHz Silicon bipolar technology. The main functions carried out by the IC are: signal amplification (40 dB) and limitation, clock recovery and decision. The design is intended to achieve a complete 2.5 Gb/s receiver by using the IC and a low noise preamplifier (transimpedance stage), mounted in a DIL package. The integrated circuit comprises about 400 active devices, used both for analog and digital blocks, and uses two supply voltages of 5 and -4.5 V. The input port is decoupled by external capacitors and matched to 50 (Omega) using on-chip resistors, whereas clock and data outputs are open collector type. The die size is 2 X 2 mm2 and the chip has been packaged using a TQFP 48 pins plastic package. Measurements under 231-1 PRBS data stream have shown an input sensitivity below 5 mVpp, rms output jitter below 7 ps and total power consumption of 0.8 W.

Paper Details

Date Published: 16 September 1998
PDF: 8 pages
Proc. SPIE 3408, Broadband European Networks and Multimedia Services, (16 September 1998); doi: 10.1117/12.321886
Show Author Affiliations
Andrea Pallotta, Italtel (Italy)
Francesco Centurelli, Univ. degli Studi di Roma La Sapienza (Italy)
Francesco Loriga, Univ. degli Studi di Roma La Sapienza (Italy)
Alessandro Trifiletti, Univ. degli Studi di Roma La Sapienza (Italy)

Published in SPIE Proceedings Vol. 3408:
Broadband European Networks and Multimedia Services
Stephan Fischer; Ralf Steinmetz; Heinrich J. Stuettgen; Harmen R. van As; Roberto Vercelli, Editor(s)

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