Share Email Print

Proceedings Paper

VHDL implementation of an image processor
Author(s): Michael Kelly; Kenneth W. Hsu
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

This paper describes the design of a flexible, pipelined general image processor (GIP) using VHDL to model the top level design and functional blocks consisting of histogram [1,2,3,4,5,6], modification, convolution, halftone, error diffusion, and threshold. GIP was simulated to have a processing speed of 70 Mpixels/second. A four pixel wide image data path is used so a clock of 17.5 MHz can be used. Mentor Graphics tool suites were used to perform the simulation and synthesis of the design. The total number of gates in 1.2 (mu) CMOSN gate array was estimated to be 236 K gates, less than 1 million transistors.

Paper Details

Date Published: 18 June 1998
PDF: 12 pages
Proc. SPIE 3422, Input/Output and Imaging Technologies, (18 June 1998); doi: 10.1117/12.311078
Show Author Affiliations
Michael Kelly, Rochester Institute of Technology (United States)
Kenneth W. Hsu, Rochester Institute of Technology (United States)

Published in SPIE Proceedings Vol. 3422:
Input/Output and Imaging Technologies
Yusheng Tim Tsai; Teh-Ming Kung; Jan Larsen, Editor(s)

© SPIE. Terms of Use
Back to Top