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Proceedings Paper

Holographic memory design for a petaflop superconducting computer architecture
Author(s): Ernest Chuang; Wenhai Liu; Demetri Psaltis
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Paper Abstract

We will descrihe the role of holographic memorv in a current research effort 1 that seeks to combine ariuus advanced technologies to achieve petaflops scale computing within the next decade In addition to holographic memory. the petatlop architecture combines superconductor Rapid Single Flu-.: Quantum (RSFQ) logic. which can operate at I 00 GHz within a cryogenic cm ironmem with power consumption less than 'iO watts. a packet-switching optical network with a multi-le el strncture capable of providing interconnection among tens or thousands of pons '' ith latencies of only I 0 to 30 nanoseconds. Processor-In-Memory (PIM) technology. and a multithreaded hierarchical structure (see Figure I) to allow the processors to access a high capacitv memnrv vhile compensating for the latenc)· problem inherent in such a system.

Paper Details

Date Published: 22 May 1998
PDF: 3 pages
Proc. SPIE 3490, Optics in Computing '98, (22 May 1998); doi: 10.1117/12.308959
Show Author Affiliations
Ernest Chuang, California Institute of Technology (United States)
Wenhai Liu, California Institute of Technology (United States)
Demetri Psaltis, California Institute of Technology (United States)

Published in SPIE Proceedings Vol. 3490:
Optics in Computing '98
Pierre H. Chavel; David A. B. Miller; Hugo Thienpont, Editor(s)

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