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Proceedings Paper

Methodology for the optimization of an i-line lithographic process for defect reduction
Author(s): Khoi A. Phan; Gurjeet S. Bains; David Ashby Steele; Jonathan A. Orth; Ramkumar Subramanian
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Paper Abstract

As device geometries shrink into the sub-half micron regime, controlling and reducing defect levels becomes increasingly important in both R&D and Manufacturing environments. Any delay in addressing the causes and cures of these yield killers can prolong the development cycle and production release of new product technologies. However, defect evaluation for a new lithography process on product wafers is difficult due to metrology limitation, substrate noises and previous layer defects. This problem is particularly pronounced for backend layers where differences in the metal grain sizes and reflectivity can confound defect inspection tools and can be picked up as false defects. Often yield learning is long delayed awaiting sort data, before lithographers can determine the beneficial effects of proposed manufacturing improvements. In this paper, we will discuss a methodology for optimizing an I-line lithographic process with the aid of a photo defect monitor. Clean Silicon wafers were fully processed through a photocluster cell to simulate the actual processing conditions for the product, then inspected on a KLA 2132 for pattern defects. An in-line low voltage SEM system was used to review and to classify defect types. In a case study presented here, post develop residue was found to be the predominant defect for a new I-line resist used in the backend layers of the 0.25 micrometer process technology. The resolution of the resist residue deposition problem was commenced by evaluating different processes with multiple puddles/rinses for their defect densities. Based on this work, a low defect developer process was chosen for further study. Other process variables such as resist profile, CD uniformity and Etch bias as well as electrical defect parameters were compared between the old and the new processes. The goal is to demonstrate that given equal performance in all other respects, a quick implementation of this new low defect process, prior to the sort yield confirmation, would not have any detrimental effect on device yield. An example of a non- killer defect, water stain droplets, discovered during the defect review will be shown. Further refining of the dry cycle in the process eliminated this cosmetic defect. Finally, the KLA defect trend chart will show an improvement in defect density with the new develop process.

Paper Details

Date Published: 8 June 1998
PDF: 12 pages
Proc. SPIE 3332, Metrology, Inspection, and Process Control for Microlithography XII, (8 June 1998); doi: 10.1117/12.308739
Show Author Affiliations
Khoi A. Phan, Advanced Micro Devices, Inc. (United States)
Gurjeet S. Bains, Advanced Micro Devices, Inc. (United States)
David Ashby Steele, Advanced Micro Devices, Inc. (United States)
Jonathan A. Orth, Advanced Micro Devices, Inc. (United States)
Ramkumar Subramanian, Advanced Micro Devices, Inc. (United States)

Published in SPIE Proceedings Vol. 3332:
Metrology, Inspection, and Process Control for Microlithography XII
Bhanwar Singh, Editor(s)

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