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Proceedings Paper

Winner/loser-take-all circuits on SOI technology for neural network classification
Author(s): Tuan A. Duong; Chris Saunders; Tri Ngo; Taher Daud
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Paper Abstract

High connectivity of artificial neural network chip- embodiments combined with currently emerging 3-dimensionally stacked multichip modules for real-time applications of target classification require a scrutiny for low power technology insertion. Conventional CMOS high power consumption limits the allowable density of synapse/neuron elements. However Silicon-On-Insulator (SOI) technology has the potential for successful implementation of high density neural network because of the following unique features: (a) Operating voltage is reduced 3-fold from 5 to 1.5 volts, reducing power requirements by 9-fold; (b) Reduced substrate offers reduced capacitance and power and an increased speed; and, (c) Latch-up phenomenon is eliminated. Here we describe two practical winner/loser-take-all (W/LTA) circuits fabricated with 0.25 micrometer fully depleted SOI technology that are useful for neural networks and as compared to other such circuits offer considerable advantage of speed and performance. SPICE circuit simulations show that up to 9-bit resolution can be obtained between a winner and a loser input and with two cascaded circuits. Final characterization tests prove that constructing circuit elements from SOI technology would allow us to build large size neural networks for practical applications.

Paper Details

Date Published: 25 March 1998
PDF: 11 pages
Proc. SPIE 3390, Applications and Science of Computational Intelligence, (25 March 1998); doi: 10.1117/12.304827
Show Author Affiliations
Tuan A. Duong, Jet Propulsion Lab. (United States)
Chris Saunders, Irvine Sensors Corp. (United States)
Tri Ngo, Jet Propulsion Lab. (United States)
Taher Daud, Jet Propulsion Lab. (United States)

Published in SPIE Proceedings Vol. 3390:
Applications and Science of Computational Intelligence
Steven K. Rogers; David B. Fogel; James C. Bezdek; Bruno Bosacchi, Editor(s)

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