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Proceedings Paper

Technology mapping for hot-carrier reliability enhancement
Author(s): Zhan Chen; Israel Koren
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Paper Abstract

As semiconductor devices enter the deep sub-micron era, reliability has become a major issue and challenge in VLSI design. Among all the failure mechanisms, hot-carrier effect is one of those which have the most significant impact on the long-term reliability of high-density VLSI circuits. In this paper, we address the problem of minimizing hot-carrier effect during the technology mapping stage of VLSI logic synthesis. We first present a logic-level hot-carrier model, and then, based on this model, we propose a technology mapping algorithm for hot-carrier effect minimization. The proposed algorithm has been implemented in the framework of the Berkeley logic optimization package SIS. Our results show that an average of 29. 1% decrease in hot-carrier effect can be achieved by carefully choosing logic gates from cell libraries to implement given logic functions for a set of benchmarks. It has also been observed that the best design for hot-carrier effect minimization does not necessarily coincide with the best design for low power, which has long been considered as a rough measure for VLSI reliability.

Paper Details

Date Published: 11 September 1997
PDF: 9 pages
Proc. SPIE 3216, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis III, (11 September 1997); doi: 10.1117/12.284706
Show Author Affiliations
Zhan Chen, Univ. of Massachusetts/Amherst (United States)
Israel Koren, Univ. of Massachusetts/Amherst (United States)

Published in SPIE Proceedings Vol. 3216:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis III
Ali Keshavarzi; Sharad Prasad; Hans-Dieter Hartmann, Editor(s)

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