As process complexity and number of plasma processing steps increase, process-induced charging damage becomes an emerging issue in continuously scaling device manufacturing. It is important, therefore, to be able to pinpoint most of potential sources of plasma charging-induced damage. The most commonly used approach involves processing and testing of several modules of antenna-type transistors, with charge sensitive antennas defined and exposed to plasma at various stages of processing. Subsequent analysis of damage allows determination of the processing level at which most of damage occurred. This work presents an alternative and complementary approach to assess potential sources of charging damage. This approach is based on in-line testing of gate oxide integrity of a MOS transistor structure with a charge collecting antenna. Gate oxide integrity tests performed after poly-silicon salicidation and after metal-1 level are used to separate the effect of poly etch and inter-layer dielectric deposition. It is shown that by the in-line testing of silicided poly antennas the effect of charging damage due to plasma-enhanced chemical vapor deposition (PECVD) of oxide can be unambiguously determined. The fingerprint of PECVD-induced charging is further documented by the surface charge analysis performed on oxidized silicon wafers exposed to PECVD oxide deposition.

Date Published: 2 September 1997
PDF: 8 pages
Proc. SPIE 3215, In-Line Characterization Techniques for Performance and Yield Enhancement in Microelectronic Manufacturing, (2 September 1997); doi: 10.1117/12.284672

Published in SPIE Proceedings Vol. 3215:
In-Line Characterization Techniques for Performance and Yield Enhancement in Microelectronic Manufacturing
Damon K. DeBusk; Sergio A. Ajuria, Editor(s)