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Proceedings Paper

Fast push at polysilicon deposition to reduce intrapoly oxide
Author(s): Judith B. Barker; Richard McCloskey
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Paper Abstract

The polysilicon process had a problem with 15% higher average class probe sheet resistance on wafers running in the top furnace position at gate polysilicon and receive 'sandwich' polysilicon (thin poly deposition followed by gate poly deposition), than wafers that run in center and bottom of the furnace. The higher sheet resistance is caused by a thicker intrapoly oxide that grows between the thin polysilicon and the gate polysilicon on wafers in the top furnace position. By increasing the push speed from 25 minutes to 5 minutes and increasing the N2 purge during push, the intrapoly oxide was minimized and the class probe polysilicon sheet resistance distribution was tightened by over 50%. The fast push process also tightened the linear N-channel threshold voltage distribution by approximately 10%.

Paper Details

Date Published: 25 August 1997
PDF: 6 pages
Proc. SPIE 3213, Process, Equipment, and Materials Control in Integrated Circuit Manufacturing III, (25 August 1997); doi: 10.1117/12.284633
Show Author Affiliations
Judith B. Barker, Motorola (United States)
Richard McCloskey, Motorola (United States)

Published in SPIE Proceedings Vol. 3213:
Process, Equipment, and Materials Control in Integrated Circuit Manufacturing III
Abe Ghanbari; Anthony J. Toprac, Editor(s)

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