Share Email Print

Proceedings Paper

Effect of local interconnect etch-stop layer on channel hot-electron degradation
Author(s): Jon Cheek; Homi E. Nariman; Dirk Wristers; Deepak Nayak; Ming-Yin Hao
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Routine use of an etch-stop layer during semiconductor processing favors circuit density and performance through the use of local interconnect and similar damascene processes, and also allows the use of manufacturable etch recipes. Previous studies have demonstrated that post transistor definition, topside passivation and deposition techniques can significantly impact device degradation characteristics. This work further investigates the choice of local interconnect etch-stop layer and its effect on channel hot-electron degradation. A reduction in channel hot-electron degradation is demonstrated through the use of N2O anneal gate oxide, and using experimental data a possible degradation mechanism, caused by the presence of the etch-stop layer, is identified. A brief review of the compatibility of etch-stop layers with high performance 0.3 micrometer CMOS devices is presented through interface state and hot-electron stress measurements.

Paper Details

Date Published: 27 August 1997
PDF: 7 pages
Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); doi: 10.1117/12.284601
Show Author Affiliations
Jon Cheek, Advanced Micro Devices, Inc. (United States)
Homi E. Nariman, Advanced Micro Devices, Inc. (United States)
Dirk Wristers, Advanced Micro Devices, Inc. (United States)
Deepak Nayak, Advanced Micro Devices, Inc. (United States)
Ming-Yin Hao, Advanced Micro Devices, Inc. (United States)

Published in SPIE Proceedings Vol. 3212:
Microelectronic Device Technology
Mark Rodder; Toshiaki Tsuchiya; David Burnett; Dirk Wristers, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?