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Proceedings Paper

Wafer-scale modeling of pattern effect in oxide chemical mechanical polishing
Author(s): Dennis O. Ouma; Brian Stine; Rajesh Divecha; Duane S. Boning; James E. Chung; Gregory B. Shinn; Iqbal Ali; John Clark
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Paper Abstract

Dielectric film thickness variation arising from layout pattern dependency remains a major concern in oxide CMP. The severity of the pattern density effect is a function of the die location on the wafer, thus a combined wafer/die pattern dependent polishing model is required to fully assess the effectiveness of the process for a given planarization requirement. In this work, a two stage modeling methodology which accounts for both wafer-scale variation and within-die pattern dependencies, as well as their interaction, is developed. The effectiveness of the methodology is demonstrated over a range of polishing process conditions and consumable choices. We find that the integrated wafer/die CMP model accurately predicts the resulting increase or decrease in die-level pattern dependencies as a function of die position on the wafer.

Paper Details

Date Published: 27 August 1997
PDF: 12 pages
Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); doi: 10.1117/12.284597
Show Author Affiliations
Dennis O. Ouma, Massachusetts Institute of Technology (United States)
Brian Stine, Massachusetts Institute of Technology (United States)
Rajesh Divecha, Massachusetts Institute of Technology (United States)
Duane S. Boning, Massachusetts Institute of Technology (United States)
James E. Chung, Massachusetts Institute of Technology (United States)
Gregory B. Shinn, Texas Instruments Inc. (United States)
Iqbal Ali, Texas Instruments Inc. (United States)
John Clark, Texas Instruments Inc. (United States)

Published in SPIE Proceedings Vol. 3212:
Microelectronic Device Technology
Mark Rodder; Toshiaki Tsuchiya; David Burnett; Dirk Wristers, Editor(s)

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