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Proceedings Paper

0.18-um gate length CMOS devices with N+ polycide gate for 2.5-V application
Author(s): Jeong Yeol Choi; Eric Zhang; Chung Chyung Han
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Paper Abstract

Single N+ polycide gate CMOS process has been scaled to the sub-0.2 micrometer gate-length regime. Estimated worst-case hot-carrier effect was 7% degradation in N-IDSAT for 10 years of continuous operation at 2.8 V. Being a buried channel device, P-MOSFETs presents a trade-off between VT adjustment and CD margin. It was manifested by the gate-to-drain overlap which increases as VT becomes less negative with more channel implant doses. We found that the relationship between gate-to- drain overlap and PMOS VT was almost independent of the n-well doping and source/drain junction depth. This indicates that the buried channel of P-MOSFETs acts as an extension to the source/drain. For VT equals 0.5 V, gate-to-drain overlap was 0.04 micrometer, and the n-well doping was twice of p-well doping for the same gate length, in order to account for the shorter effective channel length.

Paper Details

Date Published: 27 August 1997
PDF: 6 pages
Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); doi: 10.1117/12.284595
Show Author Affiliations
Jeong Yeol Choi, Integrated Device Technology (United States)
Eric Zhang, Integrated Device Technology (United States)
Chung Chyung Han, Integrated Device Technology (United States)

Published in SPIE Proceedings Vol. 3212:
Microelectronic Device Technology
Mark Rodder; Toshiaki Tsuchiya; David Burnett; Dirk Wristers, Editor(s)

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