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Proceedings Paper

Analyzing the tolerance and controls on critical dimensions and overlays as prescribed by the National Technology Roadmap for Semiconductors
Author(s): Syed A. Rizvi
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Paper Abstract

Continued demands on shrinking features with tighter tolerance on Critical Dimensions (CDs) and overlays are placing stringent requirements on parameters that are essentially the building blocks of the metrologies for CDs and overlays. This paper conducts a reality check on the precision and error budgets assigned to CD and overlay controls by the National Technology Roadmap for Semiconductors in light of constraints on parameters that are fundamental to the above measurements.

Paper Details

Date Published: 14 August 1997
PDF: 6 pages
Proc. SPIE 3183, Microlithographic Techniques in IC Fabrication, (14 August 1997); doi: 10.1117/12.280543
Show Author Affiliations
Syed A. Rizvi, Photronics Inc. (United States)

Published in SPIE Proceedings Vol. 3183:
Microlithographic Techniques in IC Fabrication
Soon Fatt Yoon; Raymond Yu; Chris A. Mack, Editor(s)

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