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Proceedings Paper

Application of rigorous topography simulation for modeling of defect propagation/growth in VLSI fabrication
Author(s): Xiaolei Li; Mahesh Reddy; Andrzej J. Strojwas; Linda Milor; YungTao Lin
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Paper Abstract

Particulate contamination deposited on silicon wafers is typically the dominant reason for yield loss in VLSI manufacturing. The transformation of contaminating particles into defects and then electrical faults is a very complex process which depends on the effect location, size, material and the underlying IC topography. A rigorous 2D topography simulator based on the photolithography simulator METROPOLE, has been developed to allow the prediction and correlation of the critical physical parameters of contamination in the manufacturing process to device defects. The results of a large number of defect samples simulated using the above approach were compared with data gathered from the AMD- Sunnyvale fabline. A good match was obtained indicating the accuracy of this method which provided a framework for developing contamination to defect propagation/growth macromodels.

Paper Details

Date Published: 7 July 1997
PDF: 10 pages
Proc. SPIE 3050, Metrology, Inspection, and Process Control for Microlithography XI, (7 July 1997); doi: 10.1117/12.275924
Show Author Affiliations
Xiaolei Li, Carnegie Mellon Univ. (United States)
Mahesh Reddy, Carnegie Mellon Univ. (United States)
Andrzej J. Strojwas, Carnegie Mellon Univ. (United States)
Linda Milor, Advanced Micro Devices, Inc. (United States)
YungTao Lin, Advanced Micro Devices, Inc. (United States)

Published in SPIE Proceedings Vol. 3050:
Metrology, Inspection, and Process Control for Microlithography XI
Susan K. Jones, Editor(s)

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