Share Email Print

Proceedings Paper

Efficient hardware structure for various binarization algorithms
Author(s): Jae Ho Kim; Young Hoon Jeong; Chae Kwan Lee; Chang Dae Park
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

In this paper, a novel and unified hardware structure to implement various binarization algorithms is proposed. It is designed to perform: 1) simple thresholding, 2) high pass filtering, 3) dithering, 4) blue noise masking, 5) error diffusion, 6) threshold nodulated error diffusion, and 7) edge enhanced error diffusion. In general, these algorithms have been implemented with several logic blocks. We found that a single data path architecture can be used for implementing those algorithms. A new structure is designed to have same data-flow that can share the blocks. All processing is possible in the proposed unified architecture which is based on the threshold modulated and edge enhanced error diffusion scheme. This structure has error filter coefficient registers, error memory, threshold memory, and arithmetic units, etc. This paper shows that the proposed hardware structure reduces the number of gates efficiently. The hardware design and debugging complexity is reduced by the unified control logic and data path.

Paper Details

Date Published: 4 April 1997
PDF: 8 pages
Proc. SPIE 3018, Color Imaging: Device-Independent Color, Color Hard Copy, and Graphic Arts II, (4 April 1997); doi: 10.1117/12.271606
Show Author Affiliations
Jae Ho Kim, Pusan National Univ. (South Korea)
Young Hoon Jeong, Pusan National Univ. (South Korea)
Chae Kwan Lee, Pusan National Univ. (South Korea)
Chang Dae Park, Pusan National Univ. (South Korea)

Published in SPIE Proceedings Vol. 3018:
Color Imaging: Device-Independent Color, Color Hard Copy, and Graphic Arts II
Giordano B. Beretta; Reiner Eschbach, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?