Share Email Print

Proceedings Paper

Versatile processor arrays based on segmented optical buses
Author(s): Yueming Li; Si Qing Zheng; Xiangyang Yang
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

We explore the potential of using optical waveguides and switches to build high performance parallel processing systems by introducing a new class of parallel computing architectures. This class of architectures are based on a special kind of reconfigurable buses called segmented buses. A segmented bus is a bus that can be dynamically partitioned into segments, called sub-buses, under program control. Such a bus can be used as a basic building block for constructing powerful parallel architectures. We show that parallel architectures based on segmented buses are versatile by embedding parallel communication patterns supported by a wide variety of networks such as linear array, ring, complete binary tree, X-tree, mesh-of-trees, multidimensional mesh, torus, multigrid and pyramid into segmented bus based architectures, and show that all these networks can be simulated with small slowdown factors.

Paper Details

Date Published: 4 April 1997
PDF: 11 pages
Proc. SPIE 3005, Optoelectronic Interconnects and Packaging IV, (4 April 1997);
Show Author Affiliations
Yueming Li, Louisiana State Univ. (United States)
Si Qing Zheng, Louisiana State Univ. (United States)
Xiangyang Yang, Univ. of New Orleans (United States)

Published in SPIE Proceedings Vol. 3005:
Optoelectronic Interconnects and Packaging IV
Ray T. Chen; Peter S. Guilfoyle, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?