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Proceedings Paper

Experimental performance of an ATM-based buffered hyperplane CMOS-SEED smart pixel array
Author(s): Stefan K. Griebel; M. Richardson; K. E. Devenport; Harvard Scott Hinton
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Paper Abstract

An ATM-based buffered HyperPlane smart pixel array (SPA) utilizing the Hybrid CMOS-SEED technology has been designed, fabricated, and tested. Multiple quantum well p-i-n photodiodes (SEEDs) are used as the optoelectronic interface in the SPA. The SPA consists of a 4 X 9 array of smart pixels comprised of 4 parallel ATM node channels. The chip fabricated is an experimental version extensible to a 256 X 256 array for implementing an ATM-based HyperPlane switching architecture on a free space optical backplane. Experimental performance of the SPA is presented.

Paper Details

Date Published: 4 April 1997
PDF: 3 pages
Proc. SPIE 3005, Optoelectronic Interconnects and Packaging IV, (4 April 1997); doi: 10.1117/12.271093
Show Author Affiliations
Stefan K. Griebel, Univ. of Colorado/Boulder (United States)
M. Richardson, Univ. of Colorado/Boulder (United States)
K. E. Devenport, Univ. of Colorado/Boulder (United States)
Harvard Scott Hinton, Univ. of Colorado/Boulder (United States)

Published in SPIE Proceedings Vol. 3005:
Optoelectronic Interconnects and Packaging IV
Ray T. Chen; Peter S. Guilfoyle, Editor(s)

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