Over the last decade, the video camera has become a common diagnostic/tool for many scientific, industrial and medical applications. The amount of data collected by video capture systems can be enormous. For example, standard NTSC video requires 5 MBytes/sec, with many groups wanting higher resolution either in bit-depth, spatial resolution and/or frame speed. Despite great advances in video capture systems developed for the mass media and teleconferencing markets, the smaller markets of scientific and industrial applications have been ignored. This is primarily due to their need to maintain the independent nature of each camera system and to maintain the high quality of the video data. Many of the commercial systems are capable of digitizing a single camera (B/W or color) or multiple synchronized B/W cameras using an RGB color video capture chip set. In addition, most manufacturers utilize lossy compression to reduce the bandwidth before storing the data to disk. To address the needs of the scientific community, a high- performance data and video recorder has been developed. This system utilizes field programmable gate arrays (FPGAs) to control the analog and digital signals and to perform real- time lossless compression on the incoming data streams. Due to the flexibility inherent in the system, it is able to be configured for a variety of camera resolutions, frame rates and compression algorithms. In addition, alternative general purpose data acquisition modules are also being incorporated into the design. The modular design of the video/data recorder allows the carrier components to be easily adapted to new bus technology as it becomes available or the data acquisition components to be tailored to a specific application. Details of the recorder architecture are presented along with examples applied to thermonuclear fusion experiments. A lossless compression ratio of 3:1 has been obtained on fusion plasma images, with further reductions expected, allowing the video recorder to capture up to ten independent video inputs and apply the compression in real-time.

Date Published: 17 January 1997
PDF: 10 pages
Proc. SPIE 3021, Multimedia Hardware Architectures 1997, (17 January 1997); doi: 10.1117/12.263520

Published in SPIE Proceedings Vol. 3021:
Multimedia Hardware Architectures 1997
Sethuraman Panchanathan; Frans Sijstermans, Editor(s)