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Proceedings Paper

Design of the datapath of a 16-bit RISC microprocessor using CMOS gate arrays technology
Author(s): Alfredo Olmos; F. Chavez; E. Aedo; A. Bernal; Edgar Charry
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Paper Abstract

This paper descrIbes the design of the MACONDO1 microprocessor datapath subsystems (16 bits RISC microprocessor): 16 bits ALU, shifter, special purpose registers, fetch machine and a 16 x 16 Reyster bank. These subsystems were implemented using a gate array mat'lx (sea of gates structure) based on the architecture conceived by Van Noije , and adapted to the 2 pm ful I custom technology from the European Silicon Structures (E52). In order the optimize tre gate array2efficiency a basic ccii was designed. An integration of 1270 transistors/mm a good routing flexibility and performance have been achieved. Also, a 2 jim CMOS Gate Array basic I ibrary was developed and electrically characterized. These functIons are required for designing every subsystem. ii, order to establish the relevant features of the main subsystems, a careful analysis of the data flow through the data path was realized. Special attention was given on the aritmetic loyic unit In which was used a transmission gate based logic style. From the simulation results under typical operations conditions, a propagation delay of 35 ns in its most critical path was obtained. As regards the memory cell of the register bank, a careful study of its stability under normal operation conditions was realtzed due to the existency of fixed transistors sizes. A maximum oPeration2frequency of 10 Mhz was observed. The total area of the register bank is 4 mm Finally, through a Multiproject Chip, two chips containing four bit slices of the whole system are being processed at the ES2 SiHcon Foundry (France).

Paper Details

Date Published: 1 November 1990
PDF: 9 pages
Proc. SPIE 1405, 5th Congress of the Brazilian Society of Microelectronics, (1 November 1990); doi: 10.1117/12.26310
Show Author Affiliations
Alfredo Olmos, Univ. del Valle (Colombia)
F. Chavez, Univ. del Valle (Colombia)
E. Aedo, Univ. del Valle (Colombia)
A. Bernal, Univ. del Valle (Colombia)
Edgar Charry, Univ. del Valle (Colombia)

Published in SPIE Proceedings Vol. 1405:
5th Congress of the Brazilian Society of Microelectronics
Vitor Baranauskas, Editor(s)

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