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Proceedings Paper

Two case studies for Level Sensitive Scan Design methodology
Author(s): Celso F. V. Brites; Augusto C. F. Morais
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Paper Abstract

This work intend to provide an overview of some implementation aspects of Design of Testability through Level Sensitive Scan Design (LSSD) Techniques in two different IC designs developed by the IC Design Group at IBM Brasil Hardware Technology Center. Aspects include LSSD Design Methodology, test pin overhead, logic overhead, fault coverage, and test generation effort.

Paper Details

Date Published: 1 November 1990
PDF: 8 pages
Proc. SPIE 1405, 5th Congress of the Brazilian Society of Microelectronics, (1 November 1990); doi: 10.1117/12.26309
Show Author Affiliations
Celso F. V. Brites, IBM Brasil (Brazil)
Augusto C. F. Morais, IBM Brasil (Brazil)

Published in SPIE Proceedings Vol. 1405:
5th Congress of the Brazilian Society of Microelectronics
Vitor Baranauskas, Editor(s)

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