The design of a CMOS focal plane array with 128 by 128 pixels and analog neural preprocessing is presented. Optical input to the array is provided by substrate-well photodiodes. A two-dimensional neural grid wIth next- neighbor connectivity, implemented as differential current- mode circuit, is capable of spatial low-pass filtering combined with contrast enhancement or binarization. The gain, spatial filter and nonlinearity parameters of the neural network are controlled externally using analog currents. This allows the multipliers and sigmoid transducers to be operated in weak inversion for a wide parameter sweep range as well as in moderate or strong inversion for a larger signal to pattern-noise ratio. The cell outputs are sequentially read out by an offset compensated differential switched-capacitor multiplexer with column preamplifiers. The analog output buffer is designed for pixel rates up to 1 pixel/microsecond and 2 by 100 pF load capacitance. All digital clocks controlling the analog data path are generated on-chip. The clock timing is programmable via a serial computer interface. Using 1 micrometer double-poly double-metal CMOS process, one pixel cell occupies 96 by 96 micrometer² and the total chip size is about 2.3 cm². Operating the neural network in weak inversion, the power dissipation of the analog circuitry is less than 100 mW.

Date Published: 19 December 1996
PDF: 11 pages
Proc. SPIE 2950, Advanced Focal Plane Arrays and Electronic Cameras, (19 December 1996); doi: 10.1117/12.262543

Published in SPIE Proceedings Vol. 2950:
Advanced Focal Plane Arrays and Electronic Cameras
Thierry M. Bernard, Editor(s)