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Proceedings Paper

Signed-digit online floating-point arithmetic for FPGAs
Author(s): Atakorn Tangtrakul; Benjamin Yeung; Todd A. Cook
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Paper Abstract

Many potential applications for reconfigurable computing need the dynamic range provided by floating-point arithmetic. However, doing floating-point on FPGAs is difficult because of the large amount of hardware required, particularly for multipliers. Some limited success has been obtained through digit-serial implementation of IEEE floating-point multipliers, but the IEEE representation is not easily or efficiently implemented in serial form. Therefore, we have been exploring alternate number representations. Signed-digit representations have shown some promise, since their form lends them to serial computation, which consumes much less hardware than fully parallel approaches. We show how the signed-digit representation can be used to implement floating-point arithmetic, and we present prototype implementations using Altera FPGAs.

Paper Details

Date Published: 21 October 1996
PDF: 12 pages
Proc. SPIE 2914, High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, (21 October 1996); doi: 10.1117/12.255805
Show Author Affiliations
Atakorn Tangtrakul, Rutgers Univ. (United States)
Benjamin Yeung, Rutgers Univ. (United States)
Todd A. Cook, Rutgers Univ. (United States)

Published in SPIE Proceedings Vol. 2914:
High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic
John Schewel; Peter M. Athanas; V. Michael Bove Jr.; John Watson, Editor(s)

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