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Proceedings Paper

Low-power radix 2 division algorithm with minimum add/sub operations
Author(s): Emad N. Farag; M. Anwarul Hasan; Mohamed I. Elmasry
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Paper Abstract

Reducing power consumption has become an important issue in many design problems. However, in some cases this should be done without affecting the speed of operation. In this paper we present a division algorithm which minimizes the number of add/sub operations. By splitting a single iteration of the algorithm into two steps we are able to reduce the clock period and make the execution time independent of quotient digits. The redundancy of the signed-digit quotient representation is exploited to reduce the comparison precision and use a CSA. This reduces the hardware complexity (hence lower power consumption) and reduces the propagation delay (hence faster operation). Finally, a comparison is given between the proposed and existing algorithms. The proposed algorithm reduces the power consumption by 15% over radix 4 division algorithm and by 45% over the radix 2 division algorithm.

Paper Details

Date Published: 22 October 1996
PDF: 12 pages
Proc. SPIE 2846, Advanced Signal Processing Algorithms, Architectures, and Implementations VI, (22 October 1996); doi: 10.1117/12.255450
Show Author Affiliations
Emad N. Farag, Univ. of Waterloo (Canada)
M. Anwarul Hasan, Univ. of Waterloo (Canada)
Mohamed I. Elmasry, Univ. of Waterloo (Canada)

Published in SPIE Proceedings Vol. 2846:
Advanced Signal Processing Algorithms, Architectures, and Implementations VI
Franklin T. Luk, Editor(s)

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