Share Email Print
cover

Proceedings Paper

DTCO acceleration to fight scaling stagnation
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

An efficient Pathfinding DTCO analysis flow which allows rapid block-level power, performance, and area (PPA) characterization is presented. To optimize this flow for the exploration of innovative technology-architecture definitions, i.e. new devices and their integration into functional logic cells, the time consuming task of generating and validating a process design kit (PDK) for each technology definition is eliminated by taking advantage of automated standard cell generation and direct emulation-based parasitic extraction. Further efficiency gains are obtained through a customized flow that allows a large number of place and route (PnR) experiments to be executed automatically. The efficiency of the presented Pathfinding DTCO flow is demonstrated in experiments quantifying block-level PPA changes in different implementations of finFET and CFET devices.

Paper Details

Date Published: 23 March 2020
PDF: 15 pages
Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280C (23 March 2020); doi: 10.1117/12.2554025
Show Author Affiliations
Lars Liebmann, TEL Technology Ctr., America, LLC (United States)
Daniel Chanemougame, TEL Technology Ctr., America, LLC (United States)
Peter Churchill, Synopsys, Inc. (United States)
Jonathan Cobb, Synopsys, Inc. (United States)
Chia-Tung Ho, Synopsys, Inc. (United States)
Victor Moroz, Synopsys, Inc. (United States)
Jeffrey Smith, TEL Technology Ctr., America, LLC (United States)


Published in SPIE Proceedings Vol. 11328:
Design-Process-Technology Co-optimization for Manufacturability XIV
Chi-Min Yuan, Editor(s)

© SPIE. Terms of Use
Back to Top
PREMIUM CONTENT
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?
close_icon_gray