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Proceedings Paper

Multi-varied implementations with common underpinnings in design technology co-optimization
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Paper Abstract

Fueled by higher bandwidth wireless communication and ubiquitous AI, the demand for more affordable and power efficient transistors is accelerating at a time when Dennard scaling is undeniably crawling to a halt. Escalating wafer and design cost are commonly identified as the primary culprits bringing Moore's law to its knees. However, a third component: the cost of making the wrong technology choice early in the development cycle, is equally responsible for slowing the progress of the semiconductor industry. The enormous complexity of leading edge technology nodes has been achieved incrementally over time by limiting each technology node to mostly small evolutionary steps. Forcing too much innovation in one technology node would have catastrophically disrupted the continuous learning curve. As we approach the fundamental device-physics and material-science limits of dimensional scaling, we are forced to look at far more disruptive device and interconnect innovations to achieve meaningful power-performance-area-cost (PPAC) improvement. For example, the complexity versus benefit tradeoffs of innovative 3-dimensional device architectures with non-standard power-distribution networks are so hard to quantify that rigorous yet efficient prototyping becomes indispensable even prior to committing foundry R&D resources. In this paper we present our work on developing a purpose-built suite of tools to vastly accelerate the quantitative pre-screening and optimization of technology options to help the industry maintain its relentless pace of PPAC scaling. We share several examples that demonstrate how we tune a candidate technology definition with this tool-suite. We also describe the important common technologies in successful Design Technology Co-Optimization (DTCO) flows including physical material and process modeling; electrical and circuit simulation; detailed design analysis and modification to reduce weak points; handling enormous datasets; silicon learning feedback loop and intuitive visualization.

Paper Details

Date Published: 23 March 2020
PDF: 11 pages
Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280Y (23 March 2020);
Show Author Affiliations
Kevin Lucas, Synopsys, Inc. (United States)
Victor Moroz, Synopsys, Inc. (United States)
John Kim, Synopsys, Inc. (United States)
Soo-Han Choi, Synopsys, Inc. (United States)
Tim Tsuei, Synopsys, Inc. (United States)


Published in SPIE Proceedings Vol. 11328:
Design-Process-Technology Co-optimization for Manufacturability XIV
Chi-Min Yuan, Editor(s)

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