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Proceedings Paper

X-ray metrology of nanowire/ nanosheet FETs for advanced technology nodes
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Paper Abstract

The three-dimensional architectures for field effect transistors (FETs) with vertical stacking of Gate-all-Around Nanowires provide a pathway to increased device density and superior electrical performance. However, the transition from research into manufacturing will only be successful if their feature shape, critical dimensions, and associated electrical performance are repeatable across the integrated circuit, across the wafer, and among multiple wafers. Patterning process control for these structures will require significant advances in metrology. Two techniques that are potential candidates for this purpose are Mueller Matrix Spectroscopic Ellipsometry based Scatterometry (MMSEscatterometry) and Critical Dimension Small Angle X-Ray Scattering (CDSAXS). In this work, we highlight the characterization of the Nanowire Test Structures fabricated from patterned Si/SixGe1-x/Si/SixGe1-x/Si/SixGe1-x/Si structures using CDSAXS. Preliminary experimental data shows sensitivity to the selective etching of subsurface SixGe1- x. CDSAXS diffraction data provides information in reciprocal space about line shape and periodicity as well as the amount of subsurface etching. Side lobes in the Intensity vs. Qz (structure height) data are observed around Qz positions of around 0.15 nm-1 and 0.5 nm-1 and are at the same positions in the measured and the simulated data for different amounts of SixGe1-x etch in the Nanowire Test Structures. This demonstrates its ability for successful measurement of the critical dimensions and 3D profile of the Nanowire Test Structures, which can then be extended to monitor several key process steps for Nanowire/Nanosheet FET fabrication.

Paper Details

Date Published: 20 March 2020
PDF: 7 pages
Proc. SPIE 11325, Metrology, Inspection, and Process Control for Microlithography XXXIV, 113250W (20 March 2020);
Show Author Affiliations
Madhulika Korde, SUNY Polytechnic Institute (United States)
R. Joseph Kline, National Institute of Standards and Technology (United States)
Daniel F. Sunday, National Institute of Standards and Technology (United States)
Nick Keller, Nanometrics Inc. (United States)
Subhadeep Kal, TEL Technology Ctr., America, LLC (United States)
Cheryl Alix, TEL Technology Ctr., America, LLC (United States)
Aelan Mosden, TEL Technology Ctr., America, LLC (United States)
Alain C. Diebold, SUNY Polytechnic Institute (United States)


Published in SPIE Proceedings Vol. 11325:
Metrology, Inspection, and Process Control for Microlithography XXXIV
Ofer Adan; John C. Robinson, Editor(s)

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